Various devices and connection arrangements have been used in the past to provide electrical interconnection between plural electrical paths, circuits, devices, etc.
Hierarchical levels of interconnection may be identified, as follows:
Level I. Component Level: At this level interconnection is effected within an electrical or electronic component. Examples of the component level of interconnection include metallization pattern on an integrated (IC) chip, lead bonding of the IC, and wiring of components to lead frames, terminals or component packages.
Level II. Circuit Card Level: Interconnection is provided at this level among components mounted to a rigid planar substrate. Examples include printed wiring boards, wire wrap socket panels and other metallized substrates.
Level III. Subassembly Level: Interconnection at this level is provided within an assembly produced for separate installation into a system. Examples are interconnection within backpanels, powere supplies, keyboards, switches, displays, component panels, and so on.
Level IV. Chassis Level: At this level interconnection is provided of components, corcuit cards, backpanels or subassemblies within a chassis.
Level V. System Level: This level includes interconnection of different chassis at the system level. Examples of implementation of this System Level of interconnection include wire and cable connections among and/or between plural chassis external of the chassis.
Several types of semiconductor circuites and devices are dependent on switching elements which provide a one-time programmable interconnection or open circuit. Examples are programmable read only memory (PROM), programmable array logic (PAL) and field programmable logic arrays (FPLA). The purpose of these circuits is to store an unchanging configuration of bits, such as a computer program or to connect a specific configuration of logic from a general programmable form. The switching elements used in practical devices of these types include diodes, transistors, thyristors, and fuses of various materials.
In a fusible link PROM, for example, fuses made of silicon, nickel chromium alloy or aluminum are incorporated into each cell or bit of the PROM. In its unprogrammed state, all fuses are intact representing all bits set to the same logic state (1 or 0). Writing a bit pattern into the PROM consists of addressing each cell where it is desired to change the static bit pattern and blowing a fuse at that location. This changes the location from a one to a zero or a zero to a one, depending on the definition of the background or shorted pattern. Typically, the fusing current is routed to the proper cell via active addressing logic and/or current steering diodes. The contents of the cell are read by active circuitry in the PROM device and the reesults are presented at the outputs of the memory.
In a zener diode type of PROM, the characteristics of the diode are changed by reverse biasing the diode to breakdown and increasing its power level to the point where a short circuit is formed across the diode. The presence of a 5 volt to 7 volt reverse breakdown versus the short circuit condition formed by programming is made use of in the memory to descriminate between ones and zeros.
A form of logic called programmable array logic (PAL) uses fuses to reconfigure a general purpose logic configuration into a specific form. Programming consists of opening fuses to disconnect outputs or inputs and to configure the desired logic form. A similar type of device is the field programmable logic array (FPLA) which may be considered the equivalent of a PROM without all address possibilities being decoded. In this case, fuses are blown to configure desired output response to a given set of input stimuli.
In the above-discussed circuits the switching elements generally are used in rather low current configurations. Fuses typically used in integrated circuit PROMs range from say about 50 to about 200 Ohms in their shorted condition. Even at these levels, considerable current, e.g. on the order of from say about 20 to about 200 milliamps is required to blow open a typical integrated circuit fuse. If lower impedances for the fuses are attempted, the programming current rises correspondigly. In the case of the shorted diode version of a PROM, the interconnection formed when the junction is shorted consists primarily of a very fine string of aluminum metalization. This metalization may be sufficient to give low impedances; however, the sectional area of the conducting path is typically too small to provide for passage of large currents. In addition, both the fusible link type PROMs and the shorted diode type PROMs require extensive current steering within the structure of the device to allow blowing the proper link or diode. Such circuitry then typically may be used as part of the sensing circuitry to read the contents of the memory, or in the cases of programmable logic families, may be part of the inherent structure.
When attempting to use the above switching elements in a matrix configuration, current steered programming using active elements may not be feasible. In the case of the fuse element, attempts to use a simple array of fuses without current steering may result in non-unique programming paths due to lack of uniformity of fuse impedances. Also, the series resistance of the fuse may be too high to provide a good signal interconnection path for high level signals.
Another type of irreversible semiconductor switching element useful in semiconductor PROMs is disclosed in U.S. Pat. No. 4,146,902. This patent discloses a switching element employing a high impedance polycrystalline silicon (sometimes referred to herein as polysilicon) resistor which may be irreversibly switched from a high impedance state after being once written on by the application of a programming level voltage above a thereshold voltage level. Such switching element is disclosed as a discrete device or as part of a low level programmable biasing path within the structure of a read only memory specifically determining whether a given memory cell will appear as a logic 1 or as a logic 0. Active circuitry is required to steer the programming voltage to the proper cells and to read the contents of the cells after programming. Thus, the switching element of such patent is used as a memory cell, and a semiconductor gate element for controlling the current flowing through the semiconductor switching element is combined with the former to complete a memory device. The entire disclosure of U.S. Pat. No. 4,146,902 hereby is incorporated by reference.
Tanimoto "A Novel MOS PROM Using a Highly Resistive Poly-Si Resistor," IEEE Transactions On Electron Devices, Vol. Ed. 27, No. 3, March 1980, presents another description of a memory cell like that of the '902 patent. The entire disclosure of such article also is hereby incorporated by reference.
A semiconductor memory device that uses memory cells located at cross positions of a plurality of bit lines and a plurality of word lines is disclosed in U.S. Pat. No. 4,287,569. The memory cells include an active element, e.g. a transistor, and a diode or fusible link. Such cells are intended to be specifically written to either by overloading a diode to short circuit the same or by blowing a fusible link to open the same, and the information in a given semiconductor memory device can be read out.
In commonly assigned, copending U.S. patent application Ser. Nos. 471,280 filed Mar. 2, 1983, Ser. No. 571,737 filed Jan. 18, 1984, and Ser. No. 614,275 filed May 25, 1984, are disclosed several devices and connection arrangements used, for example, as programmed or programmable programmed interconnection device. The entire disclosures of such applications , which now are presented in respective U.S. Pat. Nos. 4,588,239, 4,577,540 and 4,609,241, hereby are fully incorporated by reference.
One exemplary use of such programmed or programmable programmed device, as is described in such patent applications is to adapt the pin out configuration of one integrated circuit device to a different apparent pin out configuration to enable such device to be used in connection environment for which it may not originally have been intended. Another examplary use is as a shunt device to connect within the device one or more circuit paths, contacts, etc. in the device.
In the '275 application is disclosed a device that may be selectively programmed to determine which of plural circuits, conductive paths, or the like are to be electrically connected. In one embodiment there is a matrix formed of plural conductive paths or groups thereof in the device and "blowable" fuses, fused links, blown junctions or the like; the latter interconnect each path with a plurality of, preferably all, the others in the other groups in the matrix. The fuses, links, etc. may be blown to open respective circuits while other circuits are allowed to remain complete. As was noted above, a disadvantage with such device is that it is possible that the impedances of respective fuses may vary to such an extent that accurate programming may not be possible or may be possible only with great difficulty and with the result that some parts may have to be scrapped. Various other disadvantages of such blown fuse, blown junction, etc. types of devices are described in U.S. Pat. No. 4,146,902.